Memory arrays

ABSTRACT

A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed.

RELATED PATENT DATA

This patent resulted from a provisional application reissue applicationof U.S. Pat. No. 10,607,995, issued Mar. 31, 2020, which resulted fromU.S. patent application Ser. No. 15/973,697, filed May 8, 2018, whichclaims the benefit of U.S. Provisional Patent Application Ser. No.62/502,999, filed May 8, 2017, entitled “Memory Arrays”, naming MartinC. Roberts, Sanh D. Tang and Fred D. Fishburn as inventors, thedisclosures of which are incorporated by reference.

TECHNICAL FIELD

Embodiments disclosed herein pertain to memory arrays.

BACKGROUND

Memory is one type of integrated circuitry, and is used in computersystems for storing data. Memory may be fabricated in one or more arraysof individual memory cells. Memory cells may be written to, or readfrom, using digit lines (which may also be referred to as bit lines,data lines, or sense lines) and access lines (which may also be referredto as word lines). The sense lines may conductively interconnect memorycells along columns of the array, and the access lines may conductivelyinterconnect memory cells along rows of the array. Each memory cell maybe uniquely addressed through the combination of a sense line and anaccess line.

Memory cells may be volatile, semi-volatile, or non-volatile.Non-volatile memory cells can store data for extended periods of time inthe absence of power. Non-volatile memory is conventionally specified tobe memory having a retention time of at least about 10 years. Volatilememory dissipates, and is therefore refreshed/rewritten to maintain datastorage. Volatile memory may have a retention time of milliseconds orless. Regardless, memory cells are configured to retain or store memoryin at least two different selectable states. In a binary system, thestates are considered as either a “0” or a “1”. In other systems, atleast some individual memory cells may be configured to store more thantwo levels or states of information.

A capacitor is one type of electronic component that may be used in amemory cell. A capacitor has two electrical conductors separated byelectrically insulating material. Energy as an electric field may beelectrostatically stored within such material. Depending on compositionof the insulator material, that stored field will be volatile ornon-volatile. For example, a capacitor insulator material including onlySiO₂ will be volatile. One type of non-volatile capacitor is aferroelectric capacitor which has ferroelectric material as at leastpart of the insulating material. Ferroelectric materials arecharacterized by having two stable polarized states and thereby cancomprise programmable material of a capacitor and/or memory cell. Thepolarization state of the ferroelectric material can be changed byapplication of suitable programming voltages, and remains after removalof the programming voltage (at least for a time). Each polarizationstate has a different charge-stored capacitance from the other, andwhich ideally can be used to write (i.e., store) and read a memory statewithout reversing the polarization state until such is desired to bereversed. Less desirable, in some memory having ferroelectric capacitorsthe act of reading the memory state can reverse the polarization.Accordingly, upon determining the polarization state, a re-write of thememory cell is conducted to put the memory cell into the pre-read stateimmediately after its determination. Regardless, a memory cellincorporating a ferroelectric capacitor ideally is non-volatile due tothe bi-stable characteristics of the ferroelectric material that forms apart of the capacitor. Programmable materials other than ferroelectricmaterials may be used as a capacitor insulator to render capacitorsnon-volatile.

A field effect transistor is one type of electronic component that maybe used in a memory cell. These transistors comprise a pair ofconductive source/drain regions having a semiconductive channel regionthere-between. A conductive gate is adjacent the channel region andseparated there-from by a thin gate insulator. Application of a suitablevoltage to the gate allows current to flow from one of the source/drainregions to the other through the channel region. When the voltage isremoved from the gate, current is largely prevented from flowing throughthe channel region. Field effect transistors may also include additionalstructure, for example reversibly programmable charge storage/trapregions as part of the gate construction between the gate insulator andthe conductive gate.

One type of transistor is a ferroelectric field effect transistor(FeFET) wherein at least some portion of the gate construction (e.g.,the gate insulator) comprises ferroelectric material. The two differentpolarized states of the ferroelectric material in field effecttransistors may be characterized by different threshold voltage (V_(t))for the transistor or by different channel conductivity for a selectedoperating voltage. Again, polarization state of the ferroelectricmaterial can be changed by application of suitable programming voltages,and which results in one of high channel conductance or low channelconductance. The high and low conductance, invoked by the ferroelectricpolarization state, remains after removal of the gate programmingvoltage (at least for a time). The status of the channel can be read byapplying a small drain voltage which does not disturb the ferroelectricpolarization. Programmable materials other than ferroelectric materialsmay be used as a gate insulator to render a transistor to benon-volatile.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic sectional view of a substrate fragmentcomprising a memory array in accordance with an embodiment of theinvention.

FIG. 2 is a sectional view taken through line 2-2 in FIG. 1 , and at asmaller scale than FIG. 1 .

FIG. 3 is a sectional view taken through line 3-3 in FIG. 1 , and is atthe same smaller scale as FIG. 2 .

FIG. 4 is a sectional view taken through line 4-4 in FIGS. 2 and 3 , andat a smaller scale than FIG. 2 .

FIG. 5 is a sectional view taken through line 5-5 in FIGS. 2 and 3 , andis at the same smaller scale as FIG. 4 .

FIG. 6 is a diagrammatic sectional view of another substrate fragmentcomprising a memory array in accordance with an embodiment of theinvention.

FIG. 7 is a diagrammatic sectional view of another substrate fragmentcomprising a memory array in accordance with an embodiment of theinvention.

FIG. 8 is a diagrammatic sectional view of another substrate fragmentcomprising a memory array in accordance with an embodiment of theinvention.

FIG. 9 is a diagrammatic sectional view of another substrate fragmentcomprising a memory array in accordance with an embodiment of theinvention.

FIG. 10 is a diagrammatic sectional view of another substrate fragmentcomprising a memory array in accordance with an embodiment of theinvention, and is taken through line 10-10 in FIGS. 11 and 12 .

FIG. 11 is a sectional view taken through line 11-11 in FIG. 10 , and ata larger scale than FIG. 10 .

FIG. 12 is a sectional view taken through line 12-12 in FIG. 10 , and isat the same larger scale as FIG. 11 .

FIG. 13 is a diagrammatic perspective view of a predecessor substrate tothat shown by FIGS. 1-5 , and is taken through line 13-13 in FIG. 14 .

FIG. 14 is a sectional view taken through line 14-14 in FIG. 13 , and isat a larger scale than FIG. 13 .

FIG. 15 is a sectional view of the FIG. 13 substrate at a processingstep subsequent to that shown by FIG. 13 , and is taken through line15-15 in FIG. 16 .

FIG. 16 is a sectional view taken through line 16-16 in FIG. 15 , and isat the same larger scale as FIG. 14 .

FIG. 17 is a sectional view of the FIG. 15 substrate at a processingstep subsequent to that shown by FIG. 15 , and is taken through line17-17 in FIG. 18 .

FIG. 18 is a sectional view taken through line 18-18 in FIG. 17 , and isat the same larger scale as FIG. 14 .

FIG. 19 is a sectional view of the FIG. 17 substrate at a processingstep subsequent to that shown by FIG. 17 , and is taken through line19-19 in FIG. 20 .

FIG. 20 is a sectional view taken through line 20-20 in FIG. 19 , and isat the same larger scale as FIG. 14 .

FIG. 21 is a sectional view of the FIG. 19 substrate at a processingstep subsequent to that shown by FIG. 19 , and is taken through line21-21 in FIG. 22 .

FIG. 22 is a sectional view taken through line 22-22 in FIG. 21 , and isat the same larger scale as FIG. 14 .

FIG. 23 is a sectional view of the FIG. 21 substrate at a processingstep subsequent to that shown by FIG. 21 , and is taken through line23-23 in FIG. 24 .

FIG. 24 is a sectional view taken through line 24-24 in FIG. 23 , and isat the same larger scale as FIG. 14 .

FIG. 25 is a sectional view of the FIG. 23 substrate at a processingstep subsequent to that shown by FIG. 23 , and is taken through line25-25 in FIG. 26 .

FIG. 26 is a sectional view taken through line 26-26 in FIG. 25 , and isat the same larger scale as FIG. 14 .

FIG. 27 is a sectional view of the FIG. 25 substrate at a processingstep subsequent to that shown by FIG. 25 , and is taken through line27-27 in FIG. 28 .

FIG. 28 is a sectional view taken through line 28-28 in FIG. 27 , and isat the same larger scale as FIG. 14 .

FIG. 29 is a sectional view of the substrate as shown in FIG. 28 at aprocessing step subsequent to that shown by FIG. 28 , and is at the samelarger scale as FIG. 14 .

FIG. 30 is a sectional view of the FIG. 29 substrate at a processingstep subsequent to that shown by FIG. 29 , and is at the same largerscale as FIG. 14 .

FIG. 31 is a sectional view of the substrate as shown in FIG. 30 at aprocessing step subsequent to that shown by FIG. 30 , is taken throughline 31-31 in FIG. 32 , and is at the same scale as FIG. 13 .

FIG. 32 is a sectional view taken through line 32-32 in FIG. 31 , and isat the same larger scale as FIG. 14 .

FIG. 33 is a sectional view of the FIG. 31 substrate at a processingstep subsequent to that shown by FIG. 31 , and is taken through line33-33 in FIG. 34 .

FIG. 34 is a sectional view taken through line 34-34 in FIG. 33 , and isat the same larger scale as FIG. 14 .

FIG. 35 is a sectional view of the FIG. 33 substrate at a processingstep subsequent to that shown by FIG. 33 , and is taken through line35-35 in FIG. 36 .

FIG. 36 is a sectional view taken through line 36-36 in FIG. 35 , and isat the same larger scale as FIG. 14 .

FIG. 37 is a sectional view of the FIG. 35 substrate at a processingstep subsequent to that shown by FIG. 35 , and is taken through line37-37 in FIG. 38 .

FIG. 38 is a sectional view taken through line 38-38 in FIG. 37 , and isat the same larger scale as FIG. 14 .

FIG. 39 is a sectional view of the FIG. 37 substrate at a processingstep subsequent to that shown by FIG. 37 , and is taken through line39-39 in FIG. 40 .

FIG. 40 is a sectional view taken through line 40-40 in FIG. 39 , and isat the same larger scale as FIG. 14 .

FIG. 41 is a sectional view of the FIG. 39 substrate at a processingstep subsequent to that shown by FIG. 39 , and is taken through line41-41 in FIG. 42 .

FIG. 42 is a sectional view taken through line 42-42 in FIG. 41 , and isat the same larger scale as FIG. 14 .

FIG. 43 is a sectional view of the FIG. 41 substrate at a processingstep subsequent to that shown by FIG. 41 , and is taken through line43-43 in FIG. 44 .

FIG. 44 is a sectional view taken through line 44-44 in FIG. 43 , and isat the same larger scale as FIG. 14 .

FIG. 45 is a sectional view of the FIG. 43 substrate at a processingstep subsequent to that shown by FIG. 43 , and is taken through line45-45 in FIG. 46 .

FIG. 46 is a sectional view taken through line 46-46 in FIG. 45 , and isat the same larger scale as FIG. 14 .

FIG. 47 is a sectional view of the FIG. 45 substrate at a processingstep subsequent to that shown by FIG. 45 , and is taken through line47-47 in FIG. 48 .

FIG. 48 is a sectional view taken through line 48-48 in FIG. 47 , and isat the same larger scale as FIG. 14 .

FIG. 49 is a sectional view of the FIG. 47 substrate at a processingstep subsequent to that shown by FIG. 47 , and is taken through line49-49 in FIG. 50 .

FIG. 50 is a sectional view taken through line 50-50 in FIG. 49 , and isat the same larger scale as FIG. 14 .

FIG. 51 is a sectional view of the FIG. 49 substrate at a processingstep subsequent to that shown by FIG. 49 , and is taken through line51-51 in FIG. 52 .

FIG. 52 is a sectional view taken through line 52-52 in FIG. 51 , and isat the same larger scale as FIG. 14 .

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass memory arrays. A first exampleembodiment is shown in and described with references to FIGS. 1-5 . Suchincludes a substrate structure or construction 8 comprising a memoryarray 10 fabricated relative to a base substrate 11. Substrate 11 maycomprise any one or more of conductive/conductor/conducting (i.e.,electrically herein), semiconductive/semiconductor/semiconducting, andinsulative/insulator/insulating (i.e., electrically herein) materials.Various materials have been formed elevationally over base substrate 11.Materials may be aside, elevationally inward, or elevationally outwardof the FIGS. 1-5 —depicted materials. For example, other partially orwholly fabricated components of integrated circuitry may be providedsomewhere above, about, or within base substrate 11. Control and/orother peripheral circuitry for operating components within a memoryarray may also be fabricated, and may or may not be wholly or partiallywithin a memory array or sub-array. Further, multiple sub-arrays mayalso be fabricated and operated independently, in tandem, or otherwiserelative one another. As used in this document, a “sub-array” may alsobe considered as an array.

Construction 8 includes vertically-alternating tiers 12 and 14 ofinsulative material 16 (e.g., comprising, consisting essentially of, orconsisting of carbon-doped silicon nitride [2 to 10 atomic percentcarbon], silicon nitride, and/or doped or undoped silicon dioxidedeposited to a thickness of 200 Angstroms to 500 Angstroms) and memorycells 19, respectively. Only three memory cell outlines 19 are shown inFIG. 1 for clarity, although three complete and three partial memorycells are visible in FIG. 1 . Analogously, only six memory cell outlines19 are shown in FIGS. 2 and 3 , although more memory cells are visiblein FIGS. 2 and 3 . Memory cell tiers 14 may be of the same or differentthickness as that of insulative material tiers 12, with different andgreater thickness being shown (e.g., 500 Angstroms to 2,000 Angstroms).Construction 8 is shown as having seven vertically-alternating tiers 12and 14, although fewer or likely many more (e.g., dozens, hundreds,etc.) may be formed. Accordingly, more tiers 12 and 14 may be below thedepicted tiers and above base substrate 11 and/or more tiers 12 and 14may be above the depicted tiers.

Memory cells 19 individually comprise a transistor 25 and a capacitor34. Transistor 25 comprises a first source/drain region 20 and a secondsource/drain region 22 (e.g., conductively-doped semiconductor materialsuch as polysilicon for each) having a channel region 24 there-between(e.g., doped semiconductor material, such as polysilicon, but not to beintrinsically conductive). In some embodiments (but not shown), aconductively-doped semiconductor region and/or or an electricallysemiconductive region (e.g., LDD and/or halo regions) may be betweenchannel region 24 and one or both of source/drain regions 20 and 22.

A gate 26 or 27 (e.g., one or more of elemental metal, a mixture oralloy of two or more elementals, conductive metal compounds, andconductively-doped semiconductive materials) is operatively proximatechannel region 24. Specifically, in the depicted example, a gateinsulator material 28 (e.g., silicon dioxide, silicon nitride, hafniumoxide, other high k insulator material, and/or ferroelectric material)is between gate 26/27 and channel region 24. In one embodiment and asshown, individual memory cell tiers 14 comprise gate 26 and another gate27, with one of such gates (e.g., gate 26) being directly above theother (e.g., gate 27) in that individual memory cell tier 14. At least aportion of channel region 24 is horizontally-oriented for horizontalcurrent flow in the portion between first source/drain region 20 andsecond source/drain region 22. In the depicted example embodiment, allof channel region 24 is horizontally-oriented for horizontal currentflow there-through. Regardless, when suitable voltage is applied to gate26 and/or 27, a conductive channel can form within channel region 24proximate gate insulator material 28 such that current is capable offlowing between source/drain regions 20 and 22.

In one embodiment and as shown, channel region 24 comprises an annulus40 in a straight-line horizontal cross-section (e.g., the cross-sectionshown by FIG. 3 ). In one embodiment and as shown, gate 26 comprises anannulus 44 in a straight-line horizontal cross-section. (e.g., thecross-section shown by FIG. 2 ). In one embodiment and as shown, firstsource/drain region 20 comprises an annulus 41 in a straight-linehorizontal cross-section (e.g., the cross-section shown by FIG. 3 ). Inone embodiment and as shown, second source/drain region 22 comprises anannulus 42 in a straight-line horizontal cross-section (e.g., thecross-section shown by FIG. 3 ).

One or both of gates 26 and 27 may be part of an access line (e.g., twoaccess lines 90x and 90y being shown) interconnecting multipletransistors along a row or a column. Regardless, in one embodiment thatincludes both of gates 26 and 27, such gates are directly electricallycoupled to one. As examples, and by way of examples only, one or morestaircase regions 15 (one being shown in FIGS. 2, 3 , and 5) may beprovided at an end of or as a part of array 10. Staircase region 15 asshown comprises staggered contact openings 96 individually having aconductive via 97 (e.g., metal material) therein that directlyelectrically couples together vertically-stacked gates 26 and 27 inindividual memory cell tiers 14. Conductive vias 97 may connect with arespective conductive control and/or access line (not shown) toseparately access gate line pairs 26, 27 in each memory cell tier 14.

Capacitor 34 comprises a first electrode 46 and a second electrode 48(e.g., conductively-doped semiconductive material and/or metal materialfor each) having a capacitor insulator 50 there-between (e.g., silicondioxide, silicon nitride, hafnium oxide, other high k insulatormaterial, and/or ferroelectric material). Second capacitor electrodematerial 48 and capacitor insulator 50 are not separatelydistinguishable in FIG. 3 due to scale. First electrode 46 iselectrically coupled, in one embodiment directly electrically coupled,to first source/drain region 20. Second electrodes 48 of multiple ofcapacitors 34 in array 10 are electrically coupled, in one embodimentare directly electrically coupled, with one another. In one embodiment,all such second electrodes of all capacitors in array 10 areelectrically coupled with one another, and in one embodiment aredirectly electrically coupled with one another. In one embodiment and asshown, second electrode 48 is both directly above and directly belowfirst electrode 46 in a straight-line vertical cross-section (e.g., thecross-section depicted by FIG. 1 ). In one embodiment and as shown,first electrode 46 comprises an annulus 45 in a straight-line horizontalcross-section (e.g., the cross-section shown by FIG. 3 ), and in oneembodiment second electrode 48 comprises an annulus 53 in astraight-line horizontal cross-section (e.g., the cross-section shown byFIG. 3 ). In one embodiment and as shown, one gate 26 or 27 (e.g., 26)extends longitudinally directly above capacitor 34 in a straight-linevertical cross-section (e.g., the cross-section shown by FIG. 1 ), andin one embodiment other gate 26 or 27 (e.g., 27) extends longitudinallydirectly under capacitor 34 in a straight-line vertical cross-section(e.g., the cross-section shown by FIG. 1 ).

In one embodiment, a capacitor-electrode structure 52 (e.g., a solid orhollow pillar, a solid or hollow wall, etc.) extends elevationallythrough vertically-alternating tiers 12 and 14, with individual ofsecond electrodes 48 of individual capacitors 34 that are in differentmemory cell tiers 14 being electrically coupled, in one embodimentdirectly electrically coupled, to elevationally-extendingcapacitor-electrode structure 52. Example materials forcapacitor-electrode structure 52 are metal materials andconductively-doped semiconductor material. In one embodiment and asshown, capacitor-electrode structure 52 extends vertically or within 10°of vertical. In one embodiment and as shown, capacitor-electrodestructure 52 comprises an elevationally-extending wall 55 that islongitudinally-elongated horizontally and that directly electricallycouples the individual second capacitor together. In one embodiment,such, by way of example only, is one example of how second capacitorelectrodes 48 of multiple of capacitors 34 that are in different memorycell tiers 14 in the array may be electrically coupled with one another.In one embodiment, capacitor-electrode structure 52 is directlyelectrically coupled to a horizontally-elongated capacitor-electrodeconstruction 29 (e.g., a line or a plate) that is above or below (abovebeing shown) vertically-alternating tiers 12 and 14. Construction(s) 29may, in one embodiment, directly electrically couple together all secondelectrodes 48 within the array.

A sense line is electrically coupled, in one embodiment directlyelectrically coupled, to multiple of the second source/drain regions ofindividual of the transistors that are in different memory cell tiers.In one embodiment and as shown, a sense-line structure 56 (e.g., a solidor hollow pillar, a solid or hollow wall, etc.) extends elevationallythrough vertically-alternating tiers 12 and 14, with individual ofsecond source/drain regions 22 of individual transistors 25 that are indifferent memory cell tiers 14 being electrically coupled, in oneembodiment directly electrically coupled, thereto. In one embodiment andas shown, sense-line structure 56 extends vertically or within 10° ofvertical. In one embodiment and as shown, sense-line structure 56comprises a pillar 59. In one embodiment and as shown, sense-linestructure 56 comprises a peripheral conductively-doped semiconductivematerial 58 (e.g., poly silicon) and a central metal material core 60(e.g., titanium nitride and/or tungsten). In one embodiment, sense-linestructure 56 is directly electrically coupled to a horizontallongitudinally-elongated sense line 57 that is above or below (belowbeing shown) vertically-alternating tiers 12 and 14.

Example insulator material 47 (e.g., silicon nitride) and insulatormaterial 49 (e.g., silicon dioxide) may be provided as shown forsuitable isolation in sub-tiers of memory cell tiers 14.

An alternate embodiment construction 8a of a memory array 10 is shown inFIG. 6 . Like numerals from the above-described embodiments have beenused where appropriate, with some construction differences beingindicated with the suffix “a”. Only one tier 14a and two tiers 12 areshown for clarity. The channel region of transistor 25a comprises twochannel-region segments 24a that are spaced elevationally apart from oneanother in a straight-line vertical cross-section (e.g., thecross-section shown by FIG. 1 ). In one such embodiment, such twochannel-region segments 24a are directly electrically coupled to oneanother, and in one such embodiment as shown are so coupled by firstsource/drain region 20a. In one embodiment and as shown, secondelectrode 48a of capacitor 34a is not both directly above and directlybelow first electrode 46a in any straight-line vertical cross-section.In one embodiment and as shown, first electrode 46a is both directlyabove and directly below second electrode 48a in a straight-linevertical cross-section (e.g., the cross-section shown by FIG. 1 ). Anyother attribute(s) or aspect(s) as shown and/or described herein withrespect to other embodiments may be used.

FIG. 7 shows another example alternate embodiment construction 8b of amemory array 10, with individual memory cells comprising a transistor25b and a capacitor 34b. Like numerals from the above-describedembodiments have been used where appropriate, with some constructiondifferences being indicated with the suffix “b”. Again, only one tier14b and two tiers 12 are shown. Transistor 25b comprises only a singlegate 26 (e.g., no additional gate 27) associated with channel region 24.Such is shown as being above channel region 24, although such mayalternately be there-below. Accordingly, capacitor 34b may be consideredas being single-sided whereas capacitors 34 and 34a may be considered asbeing at least double-sided (e.g., top and bottom sided with respect tocapacitor electrode 48, 48a). Any other attribute(s) or aspect(s) asshown and/or described herein with respect to other embodiments may beused.

In one embodiment, individual of the memory cell tiers have no two ofthe memory cells that are directly above and directly below one anotherin that individual memory cell tier. For example, and by way of exampleonly, the above described embodiments with respect to FIGS. 1-7 showsuch example embodiments. Alternately, and by way of example only,individual of the memory cell tiers may comprise two of the memory cellswhere one of which is directly above the other in that individual tierof memory cells. A first example such embodiment is shown and describedwith respect to FIG. 8 and a construction 8c of a memory array 10. Likenumerals from the above-described embodiments have been used whereappropriate, with some construction differences being indicated with thesuffix “c”. Again, only one tier 14c and two tiers 12 are shown.

Individual memory cells 19 in a single tier 14c are shown as comprisinga transistor 25c and a capacitor 34c. One of memory cells 19 is aboveanother memory cell 19 in an individual tier 14c as shown in the exampleembodiment. In one embodiment as shown, each capacitor 34c shares acapacitor electrode 48c that extends to or is part ofcapacitor-electrode structure 52. Second source/drain regions 22 of thedepicted different transistors 25c may be electrically coupled, in oneembodiment directly electrically coupled, to one another for example asshown by conductive materials 58 and 60 as part of sense-line structure56. First source/drain regions 20 of each transistor 25c are notdirectly electrically coupled to one another, and are electricallycoupled, in one embodiment directly electrically coupled, withrespective first capacitor electrodes 46c. Thereby, twovertically-stacked memory cells 19 (one directly above the other) areformed within a single memory cell tier 14c. Transistor gates 26 and 27,in one embodiment, are not directly electrically coupled to one anotherwhich may enable better separate access/control with respect todifferent transistors 25c that are above and below one another within anindividual memory cell tier 14c. Any other attribute(s) or aspect(s) asshown and/or described herein with respect to other embodiments may beused.

A second example such embodiment is shown and described with respect toFIG. 9 and a construction 8d of a memory array 10. Like numerals fromthe above-described embodiments have been used where appropriate, withsome construction differences being indicated with the suffix “d”.Again, only one tier 14d and two tiers 12 are shown. Exampleconstruction 8d is very similar to construction 8c, with each memorycell 19 having a transistor 25d and capacitor 34c. Transistor 25ddiffers from transistor 25c in having second source/drain regions 22dthat integrally connect with one another elevationally along and asidesense-line structure 56. Still, individual memory cell tiers 14dcomprise two of memory cells 19 where one of such is directly above theother in that individual tier of memory cells.

In one embodiment that includes both of gates 26 and 27, such gates arenot directly coupled to one another. For example, such an embodiment isshown and described with respect to FIGS. 10-12 and a construction 8e ofa memory array. Like numerals from the above-described embodiments havebeen used where appropriate, with some construction differences beingindicated with the suffix “e”. Staircase region 15e comprises staggeredcontact openings 96e individually having a conductive via 97e thereinthat separately extend to different individual gates 26 and 27 inindividual memory cell tiers 14, thereby not directly coupling togethergates 26 and 27 in individual memory cell tiers 14.

The above example structures may be manufactured by any existing oryet-to-be-developed techniques. One example technique of manufacturingthe embodiment shown by FIGS. 1-5 is described with reference to FIGS.13-52 . Like numerals from the above-described embodiments have beenused for predecessor construction(s), regions, and like/predecessormaterials thereof.

FIGS. 13 and 14 show an example portion of a predecessor to theconstruction or stack of FIGS. 1-5 . The person of skill in the art mayselect any suitable different combinations of materials recognizing, inaccordance with the continuing description, that certain materials willbe etched selectively relative to other materials in the example method.As examples, and consistent with those described above, example material16 for insulative-material tiers 12 is carbon-doped silicon nitride (2to 10 atomic percent carbon). An example thickness for insulativematerial 16 is 200 to 500 Angstroms. Construction 8 includes a stack ofmaterials or layers 26, 47, 49, 47, and 27 (top-to-bottom), and each ofwhich may be considered as a sub-tier within what will be memory celltiers 14. Example thickness for each of materials 26, 47, and 27 is 100to 400 Angstroms, with example gate materials 26 and 27 being n+conductively-doped polysilicon. An example insulator material 47 issilicon nitride. Materials 26 and/or 27 may be sacrificial and replacedby conductively-doped semiconductive material and/or metal material. Anexample insulator material 49 is silicon dioxide, with an examplethickness being 300 to 600 Angstroms. Construction 8 has been patternedto form staircase region 15 whereby individual gate materials 26 and 27in individual memory cell tiers 14 form uppermost surfaces of so-called“stairs” that may subsequently be upwardly-exposed as will becomeapparent from the continuing discussion. Examplesilicon-dioxide-insulator material 49 is atop the stairs in staircaseregion 15.

Referring to FIGS. 15 and 16 , openings 33 have been formed in andthrough the depicted stack of materials in an offset or staggeredmanner. The centers of example openings 33 are centered relative to whatwill be the centers of sense-line structures 56 (not shown) and annuli40, 41, 42, and 44 (not shown).

Referring to FIGS. 17 and 18 , substrate construction 8 of FIGS. 15 and16 has been subjected to suitable etching whereby material 49 has beenetched laterally/radially selectively relative to the other depictedmaterials effective to widen openings 33 within memory cell tiers 14.With respect to the above example materials, an example etchingchemistry is dilute HF. An example uppermost silicon nitride insulatorlayer 47 protects example silicon-dioxide-insulator material 49there-under from being etched in staircase region 15.

Referring to FIGS. 19 and 20 , second capacitor electrode material 48(e.g., titanium nitride at 30 to 60 Angstroms), capacitor insulator50/gate insulator 28 (e.g., silicon dioxide and/or a high k insulator at30 to 60 Angstroms), and first capacitor electrode material 46—firstsource/drain material 20 (e.g., conductively-dope polysilicon at 50 to100 Angstroms) have been deposited as shown. Second capacitor electrodematerial 48 and capacitor insulator 50/gate insulator 28 are notseparately distinguishable in FIG. 19 , nor in subsequent correspondingodd-numbered figures, due to scale. Insulator material 50/28 may besilicon dioxide that is subjected to in situ steam generationimmediately after its deposition for densification (e.g., at 650° C. to1000° C., atmospheric or sub-atmospheric pressure, and in the presenceof O₂ and H₂). Material 46/20 has been deposited sufficient to fill thelaterally-widened portions of openings 33, but ideally not sufficient tofill the central portion of the narrower part of such openings.

Referring to FIGS. 21 and 22 , material 46/20 has been etched as shownto form finished first capacitor electrode 46 and first source/drainregion 20 (and corresponding annuli 45 and 41, respectively). An exampleetching chemistry to conduct the example depicted selective etch for thestated materials is tetra-methylammonium hydroxide (TMAH).

Referring to FIGS. 23 and 24 , intrinsic or suitably-dopedchannel-material silicon 24 has been deposited and subsequently etchedback as-shown to set the channel length (e.g., 200 Angstroms) and definechannel annuli 40. An example etching chemistry for the stated materialsis TMAH.

Referring to FIGS. 25 and 26 , more silicon-oxide-insulator material 49has been deposited effective to fill the depicted recesses/gaps thatwere formed by the etching of channel material 24 shown in in FIGS. 23and 24 , followed by selective etch thereof (e.g., dilute HF) to removesuch form the main portion of openings 33.

Referring to FIGS. 27 and 28 , insulator material 50/28 has been etched,followed by etching of titanium nitride second capacitor electrodematerial 48, to remove such from being within the main portion ofopenings 33. Example etching chemistries include, respectively, diluteHF and a combination of hydrogen peroxide and sulfuric acid. Thereafter,example silicon nitride insulator material 47 has been suitably etched(e.g., using hot phosphoric acid) to remove the uppermost layer 47 andto laterally recess material 47 within memory cell tiers 14 as shown.Such also thereby exposes elevationally uppermost and elevationallylowermost surfaces of second capacitor electrode material 48 wheresilicon nitride insulator material 47 has been removed in memory celltiers 14.

Referring to FIG. 29 , example titanium nitride material 48 has beensubjected to selective etching (e.g., using sulfuric acid and hydrogenperoxide) sufficient to recess it laterally/radially as shown and toform elevational gaps/recesses between insulator material 50/28 andexample silicon nitride 47 at radially inner ends (relative to openings33) of silicon nitride 47.

Referring to FIG. 30 , insulator material 49 has been formed within theelevational gaps/recesses that were formed by the etching shown in FIG.29 . An example technique for producing the FIG. 30 construction is aconformal deposition of example silicon-dioxide-insulator material 49,followed by etch back (e.g., using dilute HF) to remove such exceptwhere received in the depicted gaps/recesses.

Referring to FIGS. 31 and 32 , more example n+ conductively-dopedpolysilicon gate material 26, 27 has been deposited to fill theremaining gaps/recesses shown in FIG. 30 , followed by selective etchingof material 26, 27 (e.g., using TMAH) to laterally recess it as shown.

Referring to FIGS. 33 and 34 , example silicon-nitride-insulatormaterial 47 has been deposited to fill the gaps that were formed by theetching shown in FIGS. 31 and 32 , followed by selective etch thereof(e.g., using hot phosphoric acid) to remove such from being within themain portion of openings 33.

Referring to FIGS. 35 and 36 , example silicon-dioxide-insulatormaterial 49 that was formed as described above with respect to FIGS. 25and 26 (not shown in FIGS. 35 and 36 ) has been removed by selectiveetching (e.g., HF). Suring such etching, some silicon-dioxide-insulatormaterial 49 in staircase region 15 may also be etched (not shown).Alternately, uppermost silicon-nitride insulator material 47 (not shown)shown in FIG. 14 may initially be sufficiently thick such that all of itis not removed in the processing shown by FIGS. 27 and 28 such that someof it remains (not shown) and protects staircase-region-silicon-oxidematerial 49 during removal of material 49 that was formed as shown inFIGS. 25 and 26 .

Referring to FIGS. 37 and 38 , second source/drain region material22/material 58 has been deposited as shown sufficient to fill the gapsformed by removing material 49 as shown in FIGS. 35 and 36 .Subsequently, metal material 60 has been deposited and planarized and/oretched back as-shown to form sense-line structures 56. Uppermostportions of materials 58 and 60 have been removed as shown and openingsformed thereby have been plugged with insulator material 49.

Referring to FIGS. 39 and 40 , a trench 89 has been formed (e.g., usinglithography and subtractive etch with or without pitch multiplication)as shown. Such effectively enables longitudinal outlines of access lines90x and 90y (not shown yet) to be formed, as well as formation ofcapacitor-electrode structures 52 (not shown yet) as will be apparentfrom the continuing discussion.

Referring to FIGS. 41 and 42 , example polysilicon material 26, 27 hasbeen selectively etched as-shown (e.g., using TMAH), thereby forming thelongitudinal outlines of access lines 90x and 90y.

Referring to FIGS. 43 and 44 , example silicon-nitride-insulatormaterial 47 has been used to plug the gaps/recesses formed by theetching shown in FIGS. 41 and 42 , and then such material 47 has beenremoved from the main portion of trenches 89.

Referring to FIGS. 45 and 46 , example silicon-dioxide-insulatormaterial 49 has been etched selectively (e.g., using HF) laterallysufficient to expose ends of second capacitor electrode material 48 asshown.

Referring to FIGS. 47 and 48 , additional second capacitor electrodematerial 48 has been deposited to fill trenches 89 and the gaps/recessesformed by the etching shown in FIGS. 45 and 46 , thus completingformation of capacitor-electrode structures 52. Horizontally-elongatedcapacitor-electrode construction 29 may fabricated at this time (e.g.,by subtractive patterning of material 48 of capacitor-electrodestructures 52).

Referring to FIGS. 49 and 50 , contact openings 96 have been formed instaircase region 15 to upwardly expose and overlap with conductive gatematerial 26 and 27 within individual memory cell tiers 14.

Referring to FIGS. 51 and 52 , contact openings 96 have been filled withconductive material which has then been planarized back to formconductive vias 97.

CONCLUSION

In some embodiments, a memory array comprises vertically-alternatingtiers of insulative material and memory cells. The memory cellsindividually include a transistor comprising first and secondsource/drain regions having a channel region there-between and a gateoperatively proximate the channel region. At least a portion of thechannel region is horizontally-oriented for horizontal current flow inthe portion between the first and second source/drain regions. Thememory cells individually include a capacitor comprising first andsecond electrodes having a capacitor insulator there-between. The firstelectrode is electrically coupled to the first source/drain region. Thesecond capacitor electrodes of multiple of the capacitors in the arrayare electrically coupled with one another. A sense-line structureextends elevationally through the vertically-alternating tiers.Individual of the second source/drain regions of individual of thetransistors that are in different memory cell tiers are electricallycoupled to the elevationally-extending sense-line structure.

In some embodiments, a memory array comprises vertically-alternatingtiers of insulative material and memory cells. The memory cellsindividually include a transistor comprising first and secondsource/drain regions having a channel region there-between and a gateoperatively proximate the channel region. At least a portion of thechannel region is horizontally-oriented for horizontal current flow inthe portion between the first and second source/drain regions. Thememory cells individually include a capacitor comprising first andsecond electrodes having a capacitor insulator there-between. The firstelectrode is electrically coupled to the first source/drain region. Acapacitor-electrode structure extends elevationally through thevertically-alternating tiers. Individual of the second electrodes ofindividual of the capacitors that are in different memory cell tiers areelectrically coupled to the elevationally-extending capacitor-electrodestructure. A sense line is electrically coupled to multiple of thesecond source/drain regions of individual of the transistors.

In some embodiments, a memory array comprises vertically-alternatingtiers of insulative material and memory cells. The memory cellsindividually include a transistor comprising first and secondsource/drain regions having a channel region there-between and a gateoperatively proximate the channel region. At least a portion of thechannel region is horizontally-oriented for horizontal current flow inthe portion between the first and second source/drain regions. Thememory cells individually include a capacitor comprising first andsecond electrodes having a capacitor insulator there-between. The firstelectrode is electrically coupled to the first source/drain region. Asense-line structure extends elevationally through thevertically-alternating tiers. Individual of the second source/drainregions of individual of the transistors that are in different memorycell tiers are electrically coupled to the elevationally-extendingsense-line structure. A capacitor-electrode structure extendselevationally through the vertically-alternating tiers. Individual ofthe second electrodes of individual of the capacitors that are indifferent memory cell tiers are electrically coupled to theelevationally-extending capacitor-electrode structure.

In some embodiments, a memory array comprises vertically-alternatingtiers of insulative material and memory cells. The memory cellsindividually include a transistor comprising first and secondsource/drain regions having a channel region there-between and a gateoperatively proximate the channel region. At least a portion of thechannel region is horizontally-oriented for horizontal current flow inthe portion between the first and second source/drain regions. Thememory cells individually include a capacitor comprising first andsecond electrodes having a capacitor insulator there-between. The firstelectrode is electrically coupled to the first source/drain region. Thesecond capacitor electrodes of multiple of the capacitors in the arrayare electrically coupled with one another. A sense line is electricallycoupled to multiple of the second source/drain regions of individual ofthe transistors that are in different memory cell tiers. Individual ofthe tiers of memory cells comprise two of the memory cells one of whichis directly above the other in that individual tier of memory cells.

In some embodiments, a memory array comprises vertically-alternatingtiers of insulative material and memory cells. The memory cellsindividually include a transistor comprising first and secondsource/drain regions having a channel region there-between and a gateoperatively proximate the channel region. At least a portion of thechannel region is horizontally-oriented for horizontal current flow inthe portion between the first and second source/drain regions. Thememory cells individually include a capacitor comprising first andsecond electrodes having a capacitor insulator there-between. The firstelectrode is electrically coupled to the first source/drain region. Thesecond capacitor electrodes of multiple of the capacitors in the arrayare electrically coupled with one another. A sense line is electricallycoupled to multiple of the second source/drain regions of individual ofthe transistors that are in different memory cell tiers. Individual ofthe tiers of memory cells comprise the gate and another gate. One of thegate and the another gate is directly above the other in that individualtier of memory cells.

In compliance with the statute, the subject matter disclosed herein hasbeen described in language more or less specific as to structural andmethodical features. It is to be understood, however, that the claimsare not limited to the specific features shown and described, since themeans herein disclosed comprise example embodiments. The claims are thusto be afforded full scope as literally worded, and to be appropriatelyinterpreted in accordance with the doctrine of equivalents.

The invention claimed is:
 1. A memory array, comprising:vertically-alternating tiers of insulative material and memory cells,the memory cells individually comprising: a transistor comprising firstand second source/drain regions having a channel region there-betweenand a gate operatively proximate the channel region, at least a portionof the channel region being horizontally-oriented for horizontal currentflow in the portion between the first and second source/drain regions;and a capacitor comprising first and second electrodes having acapacitor insulator there-between, the first electrode beingelectrically coupled to the first source/drain region, the secondcapacitor electrodes of multiple of the capacitors in the array beingelectrically coupled with one another; and a sense-line structureextending elevationally through the vertically-alternating tiers,individual of the second source/drain regions of individual of thetransistors that are in different memory cell tiers being electricallycoupled to the elevationally-extending sense-line structure.
 2. Thearray of claim 1 wherein all of the channel region ishorizontally-oriented for horizontal current flow therethrough.
 3. Thearray of claim 1 wherein the first electrode is directly electricallycoupled to the first source/drain region.
 4. The array of claim 1wherein the individual second source/drain regions are directlyelectrically coupled to the elevationally-extending sense-lineconductive line structure.
 5. The array of claim 1 wherein thesense-line conductive line structure is directly electrically coupled toa horizontal longitudinally-elongated sense line that is above or belowthe vertically-alternating tiers.
 6. The array of claim 1 wherein thesecond capacitor electrodes of the multiple capacitors data storageelements are directly electrically coupled with one another.
 7. Thearray of claim 6 comprising an elevationally-extending wall that islongitudinally-elongated horizontally and that directly electricallycouples the second capacitor electrodes of the multiple capacitors withone another.
 8. The array of claim 1 wherein the second electrode isboth directly above and directly below the first electrode in astraight-line vertical cross-section.
 9. The array of claim 1 whereinthe second electrode is not both directly above and directly below thefirst electrode in any straight-line vertical cross-section.
 10. Thearray of claim 1 wherein the first electrode is both directly above anddirectly below the second electrode in a straight-line verticalcross-section.
 11. The array of claim 1 wherein the channel-regioncomprises two channel-region segments spaced elevationally apartrelative one another in a straight-line vertical cross-section.
 12. Thearray of claim 11 wherein the two channel-region segments are directlyelectrically coupled to one another.
 13. The array of claim 12 whereinthe two channel-region segments are directly electrically coupled to oneanother by the first source/drain region.
 14. The array of claim 1wherein individual of the tiers of memory cells comprise two of thememory cells one of which is directly above the other in that individualtier of memory cells.
 15. The array of claim 1 wherein individual of thememory cell tiers have no two of the memory cells that are directlyabove and directly below one another in that individual memory celltier.
 16. The array of claim 1 wherein individual of the tiers of memorycells comprise the gate and another gate, one of the gate and theanother gate being directly above the other in that individual tier ofmemory cells.
 17. The array of claim 1 wherein the channel regioncomprises an annulus in a straight-line horizontal cross-section. 18.The array of claim 1 wherein the first source/drain region comprises anannulus in a straight-line horizontal cross-section.
 19. The array ofclaim 1 wherein the second source/drain region comprises an annulus in astraight-line horizontal cross-section.
 20. The array of claim 1 whereinthe first electrode comprises an annulus in a straight-line horizontalcross-section.
 21. The array of claim 1 wherein the second electrodecomprises an annulus in a straight-line horizontal cross-section. 22.The array of claim 1 wherein the gate comprises an annulus in astraight-line horizontal cross-section.
 23. A memory array, comprising:vertically-alternating tiers of insulative material and memory cells,the memory cells individually comprising: a transistor comprising firstand second source/drain regions having a channel region there-betweenand a gate operatively proximate the channel region, at least a portionof the channel region being horizontally-oriented for horizontal currentflow in the portion between the first and second source/drain regions;and a capacitor comprising first and second electrodes having acapacitor insulator there-between, the first electrode beingelectrically coupled to the first source/drain region; acapacitor-electrode structure extending elevationally through thevertically-alternating tiers, individual of the second electrodes ofindividual of the capacitors that are in different memory cell tiersbeing electrically coupled to the elevationally-extendingcapacitor-electrode structure; and a sense line conductive linestructure electrically coupled to multiple of the second source/drainregions of individual of the transistors.
 24. The array of claim 23wherein the capacitor-electrode structure is directly electricallycoupled to a horizontally-elongated capacitor-electrode constructionthat is above or below the vertically-alternating tiers.
 25. The arrayof claim 23 wherein the capacitor-electrode structure comprises anelevationally-extending wall that is longitudinally-elongatedhorizontally and that directly electrically couples the individualsecond capacitor together.
 26. A memory array, comprising:vertically-alternating tiers of insulative material and memory cells,the memory cells individually comprising: a transistor comprising firstand second source/drain regions having a channel region there-betweenand a gate operatively proximate the channel region, at least a portionof the channel region being horizontally-oriented for horizontal currentflow in the portion between the first and second source/drain regions;and a capacitor comprising first and second electrodes having acapacitor insulator there-between, the first electrode beingelectrically coupled to the first source/drain region; a sense-linestructure extending elevationally through the vertically-alternatingtiers, individual of the second source/drain regions of individual ofthe transistors that are in different memory cell tiers beingelectrically coupled to the elevationally-extending sense-linestructure; and a capacitor-electrode structure extending elevationallythrough the vertically-alternating tiers, individual of the secondelectrodes of individual of the capacitors that are in different memorycell tiers being electrically coupled to the elevationally-extendingcapacitor-electrode structure.
 27. A memory array, comprising:vertically-alternating tiers of insulative material and memory cells,the memory cells individually comprising: a transistor comprising firstand second source/drain regions having a channel region there-betweenand a gate operatively proximate the channel region, at least a portionof the channel region being horizontally-oriented for horizontal currentflow in the portion between the first and second source/drain regions;and a capacitor comprising first and second electrodes having acapacitor insulator there-between, the first electrode beingelectrically coupled to the first source/drain region, the secondcapacitor electrodes of multiple of the capacitors in the array beingelectrically coupled with one another; a sense line conductive linestructure electrically coupled to multiple of the second source/drainregions of individual of the transistors that are in different memorycell tiers; and individual of the tiers of memory cells comprising twoof the memory cells one of which is directly above the other in thatindividual tier of memory cells.
 28. The array of claim 27 wherein allof the channel region is horizontally-oriented for horizontal currentflow there-through.
 29. A memory array, comprising:vertically-alternating tiers of insulative material and memory cells,the memory cells individually comprising: a transistor comprising firstand second source/drain regions having a channel region there-betweenand a gate operatively proximate the channel region, at least a portionof the channel region being horizontally-oriented for horizontal currentflow in the portion between the first and second source/drain regions;and a capacitor comprising first and second electrodes having acapacitor insulator there-between, the first electrode beingelectrically coupled to the first source/drain region, the secondcapacitor electrodes of multiple of the capacitors in the array beingelectrically coupled with one another; a sense line conductive linestructure electrically coupled to multiple of the second source/drainregions of individual of the transistors that are in different memorycell tiers; and individual of the tiers of memory cells comprising thegate and another gate, one of the gate and the another gate beingdirectly above the other in that individual tier of memory cells. 30.The array of claim 29 wherein the gate and the another gate are directlyelectrically coupled to one another.
 31. The array of claim 29 whereinthe gate and the another gate are not directly electrically coupled toone another.
 32. The array of claim 29 wherein the one of the gate andthe another gate extends longitudinally directly above the capacitor ina straight-line vertical cross-section.
 33. The array of claim 29wherein the other of the gate and the another gate extendslongitudinally directly under the capacitor in a straight-line verticalcross-section.
 34. The array of claim 33 wherein the one of the gate andthe another gate extends longitudinally directly above the capacitor inthe straight-line vertical cross-section.